The Advanced Configuration and Power Interface Standard, Revision 3.0, published Sep. 2, 2004 (“ACPI”), provides an interface for operating system control of hardware components, allowing flexible power management. The ACPI provides a method to conserve energy by transitioning unused devices into lower power states and may even place an entire system in a low-power sleeping state when desirable. A computer system in accordance with the ACPI standard may reduce power to less active components such as display screens or hard drives or may even turn available devices on or off. The ACPI standard therefore defines interface mechanisms that allow an ACPI-compatible operating system to control and communicate with an ACPI-compatible hardware platform.
According to the ACPI standard, processor power states (Cx states) are processor power consumption and thermal management states and may be further defined within a global working state, G0. Cx states include C0, C1, C2, C3 and up to Cn. Furthermore, Cx states possess specific entry and exit semantics as are briefly defined in the paragraphs below.
According to the ACPI standard, a processor may execute instructions while it is in the C0 processor power state. In the C1 power state, hardware latency is low enough that operating software does not consider the latency aspect of the state when deciding whether to use it. As defined in the standard, this state has no other software-visible effects aside from putting the processor in a non-executing power state.
The C2 power state offers improved power savings over the C1 state. The worst-case hardware latency for this state is provided by ACPI system firmware and operating software can use this information to determine when the C1 state should be used instead of the C2 state. Also as defined by the standard, the C2 state has no other software-visible effects other than putting a processor in a non-executing power state.
The C3 power state offers improved power savings over the C1 and C2 states. The worst-case hardware latency for this state is provided by ACPI system firmware and operating software can use this information to determine between states. While in the C3 state, a processor's caches maintain state but ignore any snoops, and operating software is responsible for ensuring that the caches maintain coherency. For a more detailed definition of each Cx state, see section 8.1 of the ACPI standard, Processor Power States.
A Dynamic Random Access Memory (DRAM) is a typical memory to store information. DRAMs consist of a memory cell array/matrix, where each memory cell may be coupled to one of a plurality of sense amplifiers, bit lines, and word lines. The memory cell matrix may further be subdivided into a number of banks.
DRAM memory cells consist of a single transistor and capacitor. Charge stored in a DRAM memory cell decays due to leakage current and information is eventually lost unless the charge is periodically refreshed. Since the charge must be refreshed periodically, this memory is called dynamic. An example refresh operation includes a memory controller reading data from a cell array and rewriting the data in the cell array, refreshing a capacitor in the memory cell to a previous charge. Synchronous DRAM (SDRAM) currently supports self-refresh. Self-refresh is a refresh operation executed by memory rather than a memory controller. During self-refresh a memory may use an internal oscillator to generate refresh cycles to maintain data stored in the memory cells.
Memory in self-refresh consumes less power, but there is an associated exit latency to resume normal operation. Since performance is dependant on memory access time, it can be increased when a memory controller is aware how much time it has to wake up memory and be ready when a processor needs it.
A conventional power saving approach is Rapid Memory Power Management (RMPM). RMPM is a feature in a memory controller that saves platform power by checking processor utilization. If a processor coupled with the memory controller is in C2-C4 ACPI states, it may not access memory, allowing memory to enter self-refresh. A memory controller may also turn off logic related to reading/writing memory to save power. Power can be saved due to the degree of clock gating and Delay-Locked Loop (DLL) shutdown on a controller during this state.
DRAM Row Power Management (DRPM) is another method to reduce power requirements. In DRPM, a memory row may be powered down during normal operation based on idle conditions in that row of memory. If pages for a row have all been closed at the time of power down, then a device may enter an active power down state. If pages remain open at the time of power down, the device can enter a pre-charge power down state.
Typically, memory only enters self-refresh when notified by a processor explicitly that the processor is going to be inactive, such as in ACPI states C1, C2, and C3. During C0, a processor does not explicitly state that it is going to be inactive. What is needed is a method and apparatus to enter self-refresh when not explicitly notified that coupled components not fully active.